1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and, more specifically, to a configuration of a portion related to data writing of a non-volatile semiconductor memory device performing a writing operation by introducing charges to a charge storage layer such as a floating gate. More specifically, the present invention relates to a configuration for highly precise control of threshold voltage distribution of a memory cell when multi-valued data is written.
2. Description of the Background Art
A non-volatile semiconductor memory device stores data utilizing the fact that threshold voltage of a memory cell transistor changes dependent on the amount of charges accumulated in the charge storage layer such as a floating gate. Dependent on the threshold voltage of the memory cell transistor, different amount of current flows when the memory cell is selected. By detecting the current flowing through the memory cell, data is read.
In data writing (programming), charges (electrons) are injected in accordance with information to be stored, in the charge storage layer of the memory cell transistor. Specifically, for data writing, a channel is formed at a surface of a semiconductor substrate region below the memory cell transistor, hot electrons are generated by accelerating current flowing through the channel, and the hot electrons are introduced into the charge storage layer such as the floating gate. When the amount of injected electrons increases, the threshold voltage of memory cell transistor becomes higher (when the memory cell transistor is formed of an N-channel transistor). Therefore, distribution of threshold voltages that differ in multi-steps allows storage of different data using different threshold voltages, and hence, it becomes possible to store multi-valued data in one memory cell transistor.
A non-volatile semiconductor memory device storing such multi-valued data is disclosed in Reference 1 (pamphlet of WO 2002/073623) and Reference 2 (Japanese Patent Laying-Open No. 11-330432).
In the device of Reference 1, an MOS transistor is connected in series with a memory cell transistor. The MOS transistor functions as an assist gate or a select gate that is rendered conductive in accordance with a word line potential. An assist gate forms a channel at a surface of a semiconductor region of the underlying layer in accordance with an applied voltage, and functions as a diffusion source/drain line in data reading. In data writing, the assist gate is set to a conductive state with relatively high resistance, and electrically couples adjacent memory cell transistors. A current is caused to flow from a drain region of one of the adjacent memory cell transistors to a source region of the other memory cell transistor. A high electric field generates in the channel region below the assist gate, and the high electric field produces channel hot electrons. An electric field in a vertical direction generated by a high voltage applied to a control gate (word line) of the memory cell transistor attracts the hot electrons toward the control gate, so that electrons are introduced to the floating gate.
A select transistor connects an adjacent memory cell transistor to a bit line (data line) in accordance with the word line potential, to form a path of current flow for the memory cell transistor. In data writing, a current is supplied through the select transistor to a memory cell transistor, and hot electrons are generated by a high electric field at the drain, so that the electrons are introduced into the floating gate.
According to Reference 1, in order to suppress variation in writing efficiency due to variation in threshold voltage of the MOS transistor (assist gate or select gate) connected in series with these memory cell transistors, a prescribed capacitance is connected to a drain bit line, and a write current is formed using charges accumulated in the capacitance.
In order to prevent a problem that variation in threshold voltage in the MOS transistors leads to much variation of gate current, which in turn leads to significant variation of the amount of injected charges, in Reference 1, variation in write characteristics is suppressed to be comparable to variation in electron injection efficiency and the width of threshold voltage distribution for each data value is narrowed when multi-valued data is written, so as to reduce time necessary for writing.
According to Reference 2, magnitude of a write current supplied to a memory cell is adjusted in accordance with the value of write data. This is to prevent a problem caused by a rush current in the initial stage of writing with the drain voltage kept constant, that is, to prevent the problem that excessive current flows to the memory cell and deteriorates memory cell characteristics.
In Reference 1 described above, the amount of electrons to be injected is determined using parasitic capacitance of a metal bit line and a bit line of a diffusion layer as a capacitance for storing charges at the time of writing. Therefore, in the structure disclosed in Reference 1, the amount of electrons to be injected to a selected memory cell is determined by the amount of charges accumulated in the capacitance. Accordingly, the amount of change in the threshold voltage of the selected memory cell per one writing (injection) is constant. Typically, for writing multi-valued data, the threshold voltage is increased stepwise, and the data is written accordingly.
Consider writing four-values of data “11”, “10”, “00” and “01”, respectively. Data “01” corresponds to a written (programmed) state with the highest threshold voltage and data “10” corresponds to a written (programmed) state with the lowest threshold voltage. The state storing data “11” corresponds to an erased state. The threshold voltage of memory cell transistor is adjusted in accordance with the stored data, with the erased state being the starting state.
In the structure shown in Reference 1, when a data is written, the amount of charges injected for one writing operation is fixed, as the capacitance value is fixed. Therefore, the time necessary for writing data “01” corresponding to the written state of highest threshold voltage becomes longer than the time necessary for writing data “10” corresponding to the written state of lowest threshold voltage. In order to avoid this problem, the following write sequence may be used. Following a data writing (an erasure operation) to a memory cell having the lowest threshold voltage, when data “10” of high threshold voltage is written, writing is executed also to memory cells to which other data “00” and “01” are to be written. After writing of data “10” is complete, data writing is executed again to memory cells to store data “00” and “01”, and after writing of data “00” is complete, writing is again executed to the memory cell to store data “01”.
When this write sequence is adopted and data corresponding to a state of low threshold voltage is written, it is necessary as a write-verify to perform a verifying operation on each memory cell as the object of writing for determining whether the threshold voltage is in a prescribed voltage range. Therefore, the verifying operation takes long time. Further, the number of cycles of writing to the memory cell of the highest threshold voltage becomes considerably large, which means that a high voltage for writing is applied repeatedly thereto and the number of voltage stress application increases. Thus, deterioration of memory cell characteristics would be more likely.
Reference 2 changes the amount of write current in accordance with the value of each write data, when multi-valued data is written. An arrangement utilizing a series-connection including a capacitor, a resistance and a diode is shown, as an example, for changing magnitude of a supplied write current in accordance with the write data. By using the capacitor, the amount of charges to be supplied is adjusted and the amount of write current is adjusted accordingly.
Reference 2 is directed to a cell structure of a memory cell transistor by itself, where an MOS transistor such as the assist gate is not connected in series with the memory cell transistor. The problem of variation in the amount of charges for writing derived from the variation in threshold voltage of MOS transistors such as the assist gate, that is, the problem of variation in threshold voltage of the memory cell transistors, is not at all considered.